PCI Express* Registers (D1:F0)
6 PCI Express* Registers (D1:F0)
Device 1 (D1), Function 0 (F0) contains the controls associated with the PCI Express
x16 root port that is the intended to attach as the point for external graphics. It also
functions as the virtual PCI-to-PCI bridge.
Warning:When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits.
Reserved and Preserved:
1. Reserved for future RW implementations; software must preserve value read
for writes to bits.
2. Reserved and Zero: Reserved for future R/WC/S implementations; software
must use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
Note: Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first Disable the link, then program the registers, and then re-
enable the link (which will cause a full-retrain with the new settings).
Table 6-1. PCI Express* Register Address Map (D1:F0)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
00–01h
02–03h
04–05h
06–07h
08h
VID1
DID1
Vendor Identification
8086h
29C1h
0000h
0010h
00h
RO
RO
Device Identification
PCI Command
PCICMD1
PCISTS1
RID1
RO, RW
RO, RWC
RO
PCI Status
Revision Identification
Class Code
09–0Bh
0Ch
CC1
060400h
00h
RO
CL1
Cache Line Size
RW
0Eh
HDR1
Header Type
01h
RO
18h
PBUSN1
SBUSN1
SUBUSN1
IOBASE1
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
I/O Base Address
00h
RO
19h
00h
RW
1Ah
00h
RW
1Ch
F0h
RW, RO
162
Datasheet
INTEL [ INTEL ]
