DRAM Controller Registers (D0:F0)
5.2.22
C1CYCTRKPCHG—Channel 1 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
650–651h
0000h
RO, RW
16 bits
Size:
This register provides Channel 1 CYCTRK Precharge.
Bit
Access &
Default
Description
15:11
RW
00000b
ACT To PRE Delayed (C1sd_cr_act_pchg): This configuration
register indicates the minimum allowed spacing (in DRAM clocks)
between the ACT and PRE commands to the same rank-bank.
10:6
RW
00000b
Write To PRE Delayed (C1sd_cr_wr_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the WRITE and
PRE commands to the same rank-bank. This field corresponds to tWR in
the DDR Specification.
5:2
1:0
RW
0000b
READ To PRE Delayed (C1sd_cr_rd_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
PRE commands to the same rank-bank
RW
00b
PRE To PRE Delayed (C1sd_cr_pchg_pchg): This field indicates
the minimum allowed spacing (in DRAM clocks) between two PRE
commands to the same rank.
132
Datasheet
INTEL [ INTEL ]
