DRAM Controller Registers (D0:F0)
5.1.34
TOLUD—Top of Low Usable DRAM
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
B0–B1h
0010h
RW/L, RO
16 bits
Size:
This 16 bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen
Memory (if below 4GB) are within the DRAM space defined. From the top, GMCH
optionally claims 1 to 64MBs of DRAM for internal graphics if enabled and 1 MB, 2 MB,
or 8 MB of DRAM for TSEG if enabled.
Programming Example :
C1DRB3 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Internal Graphics is enabled and Graphics Mode Select set to 32 MB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the
system. This 20 MB range at the very top of addressable memory space is lost to
APIC.
According to the above equation, TOLUD is originally calculated to:
4 GB = 1_0000_0000h
The system memory requirements are: 4 GB (max addressable space) – 1 GB (PCI
space) – 20 MB (lost memory) = 3 GB – 128 MB (minimum granularity) =
B800_0000h
Since B800_0000h (PCI and other system requirements) is less than 1_0000_0000h,
TOLUD should be programmed to B80h.
Bit
Access &
Default
Description
15:4
RW/L
001h
Top of Low Usable DRAM (TOLUD): This register contains bits
31:20 of an address one byte above the maximum DRAM memory
below 4 GB that is usable by the operating system. Address bits
31:20 programmed to 01h implies a minimum memory size of 1 MB.
Configuration software must set this value to the smaller of the
following 2 choices: maximum amount memory in the system minus
ME stolen memory plus one byte or the minimum address allocated
for PCI memory. Address bits 19:0 are assumed to be 0_0000h for
the purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is less
than the value programmed in this register.
This register must be 64 MB aligned when reclaim is enabled.
Reserved
3:0
RO
0000b
108
Datasheet
INTEL [ INTEL ]
