DRAM Controller Registers (D0:F0)
5.1.28
SMRAM—System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
9Dh
02h
RO, RW/L, RW, RW/L/K
8 bits
Size:
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
Bit
7
Access &
Default
Description
RO
0b
Reserved
6
RW/L
0b
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the
SMM space DRAM is made visible even when SMM decode is not
active. This is intended to help BIOS initialize SMM space. Software
should ensure that D_OPEN=1 and D_CLS=1 are not set at the same
time.
5
4
RW
0b
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is
not accessible to data references, even if SMM decode is active. Code
references may still access SMM space DRAM. This will allow SMM
software to reference through SMM space to update the display even
when SMM is mapped over the VGA range. Software should ensure
that D_OPEN=1 and D_CLS=1 are not set at the same time.
RW/L/K
0b
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN
is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN,
TSEG_SZ and TSEG_EN become read only. D_LCK can be set to 1 via
a normal configuration space write but can only be cleared by a Full
Reset. The combination of D_LCK and D_OPEN provide convenience
with security. The BIOS can use the D_OPEN function to initialize SMM
space and then use D_LCK to "lock down" SMM space in the future so
that no application software (or BIOS itself) can violate the integrity
of SMM space, even if the program has knowledge of the D_OPEN
function.
3
RW/L
0b
Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible
SMRAM functions are enabled, providing 128 KB of DRAM accessible
at the A0000h address while in SMM (ADSB with SMM decode). To
enable Extended SMRAM function this bit has be set to 1. Refer to the
section on SMM for more details. Once D_LCK is set, this bit becomes
read only.
2:0
RO
0b
Compatible SMM Space Base Segment (C_BASE_SEG): This field
indicates the location of SMM space. SMM DRAM is not remapped. It is
simply made visible if the conditions are right to access SMM space,
otherwise the access is forwarded to DMI. Since the GMCH supports
only the SMM space between A0000 and BFFFF, this field is hardwired
to 010.
Datasheet
103
INTEL [ INTEL ]
