DRAM Controller Registers (D0:F0)
5.1.24
PAM6—Programmable Attribute Map 6
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
96h
00h
RO, RW
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h–0EFFFFh.
Bit
Access &
Default
Description
7:6
5:4
RO
00b
Reserved
0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0E4000h to 0E7FFFh.
RW
00b
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
1:0
Reserved
RO
00b
0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0E0000h to 0E3FFFh.
RW
00b
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
100
Datasheet
INTEL [ INTEL ]
