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298596-004 参数 Datasheet PDF下载

298596-004图片预览
型号: 298596-004
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内容描述: 英特尔赛扬处理器的PGA370插槽高达1.40 GHz的0.13微米工艺 [Intel Celeron Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process]
分类和应用:
文件页数/大小: 82 页 / 1417 K
品牌: INTEL [ INTEL ]
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Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process  
Table 7. Voltage and Current Specifications (Sheet 2 of 2)  
1, 2  
Symbol  
Parameter  
Core Freq  
Min  
Typ  
Max  
Unit  
Notes  
Termination current slew  
rate  
Table  
13  
8, 9, 10 See  
Table 13  
dIvTT/dt  
A/µs  
NOTES:  
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.  
2. All specifications in this table apply only to the Celeron processor based on 0.13 micron process core.  
3. VccCORE and IccCORE supply the processor core and the on-die L2 cache.  
4. VTT must be held to 1.25 V ±9% while the AGTL bus is active. It is required that VTT be held to 1.25 V ±3%  
while the processor system bus is static (idle condition). The ±3% range is the required design target; ±9%  
will come from the transient noise added. This is measured at the PGA370 socket pins on the bottom side of  
the baseboard.  
5. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the  
processor socket pin on the soldered-side of the motherboard. VCCCORE must return to within the static  
voltage specification within 100 µs after a transient event; see the VRM 8.5 DC-DC Converter Design  
Guidelines for further details.  
6. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.  
7. The current specified is also for AutoHALT state.  
8. Maximum values are specified by design/characterization at nominal VccCORE  
.
9. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum  
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.  
10. dIcc/dt specifications are measured and specified at the PGA370 socket pins.  
11. Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output  
load ranges specified in the tables above. See VRM 8.5 Specification.  
12.Pull ups only.  
13. For frequencies beyond 1.40 GHz, refer to the latest flexible motherboard 1 extended (FMB1-E) guidelines  
available via your Intel Representative.  
14. 1.20 GHz at VccCORE = 1.475 volts and S-Spec number SL5XS.  
Table 8. Power Supply Current Slew Rate (dIcccore/dt)  
Slew Rate: 26 A Load Step  
Slew Rate (26 A): ICC at Socket  
30  
25  
20  
15  
10  
5
PWL SLew Rate Data  
Time (us) ICC at Socket (A)  
0.1  
0.15  
0.5  
1
1.5  
2
2.5  
4
3.5  
4
26.23  
23.18  
20.03  
21.10  
21.88  
22.29  
22.30  
22.07  
21.78  
21.58  
21.51  
4.5  
0
0
1
2
3
4
5
6
Table 8 contains typical slew rate data for the processor. Actual slew rate values and wave-shapes  
may vary slightly depending on the type and size of decoupling capacitors used in a particular  
implementation.  
Datasheet  
27