Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may
begin or be in progress while the processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will
stay in the Quick Start state after initialization until STPCLK# is deasserted.
2.2.5
2.2.6
HALT/Grant Snoop State
The processor will respond to snoop transactions on the system bus while in the Auto Halt or Quick
Start state. When a snoop transaction is presented on the system bus the processor will enter the
HALT/Grant Snoop state. The processor will remain in this state until the snoop has been serviced
and the system bus is quiet. After the snoop has been serviced, the processor will return to its
previous state. If the HALT/Grant Snoop state is entered from the Quick Start state, then the input
signal restrictions of the Quick Start state still apply in the HALT/Grant Snoop state, except for
those signal transitions that are required to perform the snoop.
Deep Sleep State
The Deep Sleep state is a very low power state that the processor may enter while maintaining its
context. The Deep Sleep state is entered by stopping the BCLK and BCLK# inputs to the processor
or by asserting the DPSLP# signal, while it is in the Quick Start state. Note that either one of the
methods may be used to enter Deep Sleep but not both at the same time. When BCLK and BCLK#
are stopped, they must obey the DC levels specified in Table 33.
The processor will return to the Quick Start state from the Deep Sleep state when the BCLK and
BCLK# inputs are restarted or the DPSLP# signal is deasserted. Due to the PLL lock latency, there
is a delay of up to 30 µs after the clocks have started before this state transition happens. PICCLK
may be removed in the Deep Sleep state. PICCLK should be designed to turn on when BCLK and
BCLK# turn on or DPSLP# is deasserted when transitioning out of the Deep Sleep state.
Table 2. Clock State Characteristics
Clock State
Normal
Exit Latency
Snooping?
System Uses
Normal program execution
N/A
Yes
Yes
Auto Halt
10 µs
S/W controlled entry idle mode
Through snoop, to HALT/
Grant Snoop state:
immediate
Quick Start
Yes
H/W controlled entry/exit mobile throttling
Through STPCLK#, to
Normal state: 10 µs
HALT/Grant
Snoop
A few bus clocks after
snoop completion
Yes
No
Supports snooping in the low power states
H/W controlled entry/exit mobile powered-on
suspend support
Deep Sleep 30 µs
2.2.7
Operating System Implications of Low-power States
The time-stamp counter and the performance monitor counters are not ensured to count in the
Quick Start state. The local APIC timer and performance monitor counter interrupts should be
disabled before entering the Deep Sleep state or the resulting behavior will be unpredictable.
16
Datasheet
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