Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
2.0
Ultra-Low Voltage Intel® Celeron® Processor
Features
®
®
2.1
New Features in the Ultra-Low Voltage Intel Celeron
Processor
2.1.1
100-MHz PSB With AGTL Signaling
The ULV Intel® Celeron® processor uses Assisted GTL (AGTL) signaling on the Processor System
Bus (PSB) interface. The main difference between AGTL and GTL+ used on previous Intel
processors is V
= 1.25 V for AGTL versus 1.5 V for GTL+. The lower voltage swing enables
CCT
high performance at lower power.
2.1.2
2.1.3
256-K On-die Integrated L2 Cache
The 256-K on die integrated L2 cache on the ULV Intel Celeron processor is double the L2 cache
size of previous Intel Celeron processors (0.18 µ). The L2 cache runs at the processor core speed
and the increased cache size provides superior processing power.
Data Prefetch Logic
The ULV Intel Celeron processor features Data Prefetch Logic that speculatively fetches data to the
L2 cache before an L1 cache request occurs. This reduces transactions between the cache and
system memory reducing or eliminating bus cycle penalties, resulting in improved performance.
The processor also includes extensions to memory order and reorder buffers that boost
performance.
2.1.4
2.1.5
Differential Clocking
Differential clocking requires the use of two complementary clocks: BCLK and BCLK#. Benefits
of differential clocking include easier scaling to lower voltages, reduced EMI, and less jitter. All
references to BCLK in this document apply to BCLK# also even if not explicitly stated. The ULV
Intel Celeron processor will also support Single Ended Clocking. The processor will configure
itself for Differential or Single Ended Clocking based on the waveforms detected on the BCLK and
BCLK#/CLKREF signal lines.
Signal Differences Between the Mobile Intel® Celeron®
Processor in BGA2 and Micro-PGA2 Packages and
the Ultra-Low Voltage Intel® Celeron® Processor in Micro FC-BGA
Packages
A list of new and changed signals is shown in Table 1.
Datasheet
13
INTEL [ INTEL ]
