Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management
Interrupt (SMI) handler may be to either the Normal state or the Auto Halt state. See the Intel®
Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more
information. No Halt bus cycle is issued when returning to the Auto Halt state from the System
Management Mode (SMM).
The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have
been flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle.
Transitions in the A20M# and PREQ# signals are recognized while in the Auto Halt state.
Figure 1. Clock Control States
STPCLK#1
BCLK stopped
or DPSLP#
Normal
HS=false
Quick Start
Deep Sleep 2
(!STPCLK# and !HS)
or RESET#
BCLK on
and !DPSLP#
STPCLK#1
halt
break
snoop
serviced
HLT
snoop
occurs
!STPCLK#
and HS
instruction1
snoop
occurs
Auto Halt
HS=true
HALT/Grant
Snoop
snoop
V0001-022
serviced
NOTES:
1. State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycle completes
Halt break - A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
HLT - HLT instruction executed
HS - Processor Halt State
2. Restrictions apply to the use of both methods of entering Deep Sleep. See Deep Sleep state description for
details.
2.2.4
Quick Start State
The processor is required to be configured for the Quick Start state by strapping the A15# signal
low. In the Quick Start state the processor is only capable of acting on snoop transactions generated
by the system bus priority device. Because of its snooping behavior, Quick Start may only be used
in a uniprocessor (UP) configuration.
A transition to the Deep Sleep state may be made by stopping the clock input to the processor or
asserting the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is
made only if the STPCLK# signal is deasserted.
While in this state the processor is limited in its ability to respond to input. It is incapable of
latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
Datasheet
15
INTEL [ INTEL ]
