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250686-007 参数 Datasheet PDF下载

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型号: 250686-007
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内容描述: 移动式英特尔奔腾4处理器-M [Mobile Intel Pentium4 Processor-M]
分类和应用:
文件页数/大小: 97 页 / 4754 K
品牌: INTEL [ INTEL ]
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System Bus Signal Quality Specifications  
3.  
System Bus Signal Quality Specifications  
Source synchronous data transfer requires the clean reception of data signals and their associated  
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage  
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be  
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive  
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity and can  
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and  
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI)  
effects. For these reasons, it is important that the designer work to achieve a solution that provides  
acceptable signal quality across all systematic variations encountered in volume manufacturing.  
This section documents signal quality metrics used to derive topology and routing guidelines  
through simulation and for interpreting results for signal quality measurements of actual designs.  
3.1  
System Bus Clock (BCLK) Signal Quality Specifications  
and Measurement Guidelines  
Table 27 describes the signal quality specifications at the processor pads for the processor system  
bus clock (BCLK) signals. Figure 25 describes the signal quality waveform for the system bus  
clock at the processor pads.  
Table 27. BCLK Signal Quality Specifications  
Parameter  
Min  
Max  
Unit  
Figure  
Notes1  
BCLK[1:0] Overshoot  
N/A  
N/A  
0.20  
N/A  
0.30  
0.30  
N/A  
V
V
V
V
25  
25  
25  
25  
BCLK[1:0] Undershoot  
BCLK[1:0] Ringback Margin  
BCLK[1:0] Threshold Region  
2
0.10  
NOTES:  
1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M  
frequencies.  
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute  
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This  
specification is an absolute value.  
Mobile Intel Pentium 4 Processor-M Datasheet  
51  
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