Electrical Specifications
Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group
T# Parameter
Min
Typ
Max
Unit
Figure Notes1,2,3,4
T20: Source Synchronous Data Output
Valid Delay (first data/address only)
0.20
1.20
ns
14, 15
15
5
T21: TVBD: Source Synchronous Data
Output Valid Before Strobe
0.85
0.85
1.88
1.88
0.21
0.21
0.65
ns
ns
5, 8
5, 9
5, 8
5, 9
6
T22: TVAD: Source Synchronous Data
Output Valid After Strobe
15
T23: TVBA: Source Synchronous
Address Output Valid Before Strobe
ns
14
T24: TVAA: Source Synchronous
Address Output Valid After Strobe
ns
14
T25: TSUSS: Source Synchronous Input
Setup Time to Strobe
ns
14, 15
14, 15
14, 15
14
T26: THSS: Source Synchronous Input
Hold Time to Strobe
ns
6
T27: TSUCC: Source Synchronous Input
Setup Time to BCLK[1:0]
ns
7
T28: TFASS: First Address Strobe to
Second Address Strobe
1/2
n/4
BCLK
BCLK
ns
10
T29: TFDSS: First Data Strobe to
Subsequent Strobes
15
11, 12
13
T30: Data Strobe ‘n’ (DSTBN#) Output
valid Delay
8.80
2.27
10.20
4.23
15
T31: Address Strobe Output Valid
Delay
ns
14
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source
synchronous data signals are referenced to the falling edge of their associated data strobe. Source
synchronous address signals are referenced to the rising and falling edge of their associated address strobe.
All source synchronous AGTL+ signal timings are referenced to GTLREF at the processor core.
4. Unless otherwise noted these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF
at 2/3 VCC ± 2%.
6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
of 0.3 V/ns to 4.0V /ns.
7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
respective strobe.
8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for more
information on the definitions and use of these specifications.
9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for more
information on the definitions and use of these specifications.
10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of
ADSTB#.
11.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after
the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4
BCLK period (5 ns) after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must
come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#.
13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
Mobile Intel Pentium 4 Processor-M Datasheet
37
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