Electrical Specifications
Table 19. System Bus Differential Clock Specifications
T# Parameter
System Bus Frequency
Min
Nom
Max
Unit
Figure
Notes1
100
10.2
200
6.12
6.12
700
700
MHz
ns
T1: BCLK[1:0] Period
10.0
10
2
T2: BCLK[1:0] Period Stability
T3: BCLK[1:0] High Time
T4: BCLK[1:0] Low Time
T5: BCLK[1:0] Rise Time
T6: BCLK[1:0] Fall Time
ps
3
3.94
3.94
175
175
5
5
ns
10
10
10
10
ns
ps
4
4
ps
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
3. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
4. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).
.
Table 20. System Bus Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes1,2,3
T10: Common Clock Output Valid Delay
T11: Common Clock Input Setup Time
T12: Common Clock Input Hold Time
T13: RESET# Pulse Width
0.12
0.65
0.40
1
1.55
ns
ns
ns
ms
12
12
12
13
4
5
5
10
6, 7, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF
at 2/3 VCC ± 2%.
5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
of 0.4 V/ns to 4.0 V/ns.
6. RESET# can be asserted asynchronously, but must be deasserted synchronously.
7. This should be measured after VCC and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
.
36
Mobile Intel Pentium 4 Processor-M Datasheet
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