Electrical Specifications
Table 15. PWRGOOD and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes1
VHYS
Input Hysteresis
200
300
mV
V
8
5
Input Low to High
Threshold Voltage
VT+
VT-
1/2*(Vcc+VHYS_MIN)
1/2*(Vcc-VHYS_MAX)
1/2*(Vcc+VHYS_MAX)
1/2*(Vcc-VHYS_MIN)
Input High to Low
Threshold Voltage
V
5
VOH
IOL
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
N/A
N/A
N/A
N/A
8.75
VCC
40
V
mA
µA
µA
Ω
2,3,5
6,7
9
IHI
100
500
13.75
ILO
Ron
10
4
Buffer On Resistance
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open-drain.
3. TAP signal group must comply with the signal quality specifications in Section 3.
4. Refer to I/O Buffer Models for I/V characteristics.
5. The VCC referred to in these specifications refers to instantaneous VCC
.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load shown if Figure 8.
7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 8 for the
TAP Signals.
8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs.
9. Leakage to VSS with pin held at VCC
.
10.Leakage to VCC with pin held at 300 mV.
Table 16. ITPCLKOUT[1:0] DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
Ron
Buffer On Resistance
27
46
Ω
2,3
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. See Figure 7 for ITPCLKOUT[1:0] output buffer diagram.
Mobile Intel Pentium 4 Processor-M Datasheet
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