Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362
Remote Loopback (RLOOP)
2.7.1.3
See Figure 8. When RLOOP is active, the device ignores the transmit data and clock inputs (TCLK
and TPOS/TNEG or TDATA), and bypasses the in-line encoders/decoders. The RPOS/RNEG or
RDATA outputs loop back through the transmit circuits to TTIP and TRING at the RCLK
frequency. The RLOOP command does not affect the receiver circuits which continue to output the
RCLK and RPOS/RNEG or RDATA signals received from the twisted-pair line.
In Host mode, command RLOOP by writing a 1 to bit CR2.ERLOOP. In Hardware mode, RLOOP
is commanded by setting the RLOOP pin High.
2.7.1.4
Network Loopback (NLOOP)
NLOOP can be initiated only when the Network loopback detect function is enabled. With NLOOP
detection enabled, the receiver looks for the NLOOP data patterns (00001 = enable, 001 = disable)
in the input data stream. The LXT362 responds to both framed and unframed NLOOP patterns.
When the receiver detects the NLOOP enable data pattern repeated for a minimum of five seconds,
loopback is activated. Once activated, operation is identical to Remote loopback (RLOOP).
In Host mode, setting bit CR2.ENLOOP = 1 enables NLOOP detection. In Hardware mode, setting
the RLOOP pin to Midrange enables NLOOP detection.
NLOOP is disabled upon reception of the 001 pattern for five seconds, or by activating RLOOP or
ALOOP, or by disabling NLOOP detection. Note that the LXT362 enters Dual loopback mode
(DLOOP) when both NLOOP and LLOOP functions are selected.
Figure 8. Remote Loopback
Remote Loopback with JA in Receive Path
TCLK
TPOS
TNEG
TTIP
Timing &
Control
TRING
* If Enabled
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
JA*
RRING
Remote Loopback with JA in Transmit Path
TCLK
TPOS
TNEG
TTIP
Timing &
JA*
TRING
Control
* If Enabled
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
2.7.1.5
Dual Loopback (DLOOP)
See Figure 9. In Hardware mode, DLOOP is selected by setting both the RLOOP and LLOOP pins
High. In Host mode set bits CR2.ERLOOP = 1 and CR2.ELLOOP = 1. In DLOOP mode, the
transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back through the Jitter
Datasheet
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INTEL [ INTEL ]
