Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362
Bipolar Violation Detection (BPV)
2.7.3.4
When the internal encoders/decoders are disabled or when configured in Unipolar mode, bipolar
violations are reported at the BPV pin. BPV goes High for a full clock cycle to indicate receipt of a
BPV. When the encoders/decoders are enabled, the LXT362 does not report bipolar violations due
to the line coding scheme.
2.7.4
Alarm Condition Monitoring
2.7.4.1
Loss of Signal (LOS)
The receiver LOS monitor loads a digital counter at the RCLK frequency. The count increments
with each received 0 and the counter resets to 0 on receipt of a 1. When the count reaches “n” 0s,
the LOS flag goes High, and the MCLK replaces the recovered clock at the RCLK output in a
smooth transition. For Hardware mode, the number of 0s, n = 175. In Host mode, either 175 or
2048 may be selected by setting bit CR4.LOS2048.
When the received signal has 12.5% 1’s density (16 marks in a sliding 128-bit period, with fewer
than 100 consecutive 0s), the LOS flag returns Low and the recovered clock replaces MCLK at the
RCLK output in another smooth transition.
During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar
mode). In Hardware and Host modes, the LOS pin goes High when a LOS condition occurs. In
Host mode, bit PSR.LOS =1 indicates a LOS condition, and will generate an interrupt if enabled.
2.7.4.2
Alarm Indication Signal Detection (AIS)
This function is only available in Host mode. The receiver detects an AIS pattern when it receives
fewer than three 0s in any string of 2048 bits. The device clears the AIS condition when it receives
three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
2.7.4.3
2.7.4.4
Driver Failure Monitor Open (DFMO)
This function is only available in Host mode. The DFMO bit is available in the Performance Status
Register to indicate an open condition on the lines. DFMO can generate an interrupt to the host
controller. The Transition Status Register bit TDFMO indicates a transition in the status of the bit.
Writing a 1 to ICR.CDFMO will clear or mask the interrupt.
Elastic Store Overflow/Underflow (ESOVR and ESUNF)
This function is only available in Host mode. When the bit count in the Elastic Store (ES) is within
two bits of overflowing or underflowing the ES adjusts the output clock by 1/8 of a bit period. The
ES provides an indication of overflow and underflow via bits TRS.ESOVR and TSR.ESUNF.
These are “sticky bits” and will stay set to 1 until the host controller reads the register. These
interrupts can be cleared or masked by writing a 1 to the bits ICR.CESO and ICR.CESU,
respectively.
Datasheet
27
INTEL [ INTEL ]
