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249033-001 参数 Datasheet PDF下载

249033-001图片预览
型号: 249033-001
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的T1 LH / SH收发器,用于DS1 / DSX - 1或PRI应用 [Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications]
分类和应用:
文件页数/大小: 48 页 / 789 K
品牌: INTEL [ INTEL ]
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Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications LXT362  
2.7.1  
Loopback Modes  
2.7.1.1  
Local Loopback (LLOOP)  
See Figure 5 and Figure 6. LLOOP inhibits the receiver circuits. The transmit clock and data inputs  
(TCLK and TPOS/TNEG or TDATA) loop back through the jitter attenuator (if enabled) and  
appear at RCLK and RPOS/RNEG or RDATA. Note that during LLOOP, the JASEL input is  
strictly an enable/disable control, i.e. it does not affect the placement of the JA. If the JA is enabled,  
it is active in the loopback circuit. If the JA is bypassed, it is not active in the loopback circuit.  
The transmitter circuits are unaffected by LLOOP and the LXT362 continues to transmit the  
TPOS/TNEG or TDATA inputs (or a stream of 1s if TAOS is asserted). When used in this mode,  
the transceiver can function as a stand-alone jitter attenuator.  
In Hardware mode, Local loopback (LLOOP) is selected by setting LLOOP High; in Host mode,  
by setting bit CR2.ELLOOP = 1.  
Figure 5. TAOS with LLOOP  
Datasheet  
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