LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.7.2.3
In-Band Network Loop Up or Down Code Generator
In-band Network Loop Up or Loop Down code transmission is available in Host mode only. The
Loop Up code is 00001; Loop Down code is 001. A Loop Up code transmission occurs when bits
CR2.EPAT0 = 1 and CR2.EPAT1 = 0. A Loop Down code transmission occurs when CR2.EPAT0 =
1 and CR2.EPAT1 = 1.
With this mode is active, logic errors and bipolar violations can be inserted into the transmit data
stream. Inserting a logic error requires a Low-to-High transition of the INSLER pin. If no logic or
bit errors are to be inserted, INSLER must remain Low. A Low-to-High transition on the INSBPV
pin will insert a bipolar violation, regardless of whether the device is in the Unipolar or Bipolar
mode of operation.
2.7.3
Error Insertion and Detection
2.7.3.1
Bipolar Violation Insertion (INSBPV)
The INSBPV function is available in Unipolar mode. Sampling occurs on the falling edge of
TCLK. A Low-to-High transition on the INSBPV pin inserts a BPV on the next available mark,
except in the four following situations:
• When zero suppression (B8ZS) is not violated
• When LLOOP and TAOS are both active. In this case, the BPV is looped back to the BPV pin
and the line driver transmits all ones with no violation.
• When RLOOP is active
• When NLOOP is active
Note that when the LXT362 is configured to transmit internally generated data patterns (QRSS or
NLOOP), a BPV can be inserted on the transmit pattern regardless of whether the device is in the
Unipolar or Bipolar mode of operation.
2.7.3.2
Logic Error Insertion (INSLER)
When transmission of QRSS or NLOOP Up/Down codes are active, a logic error is inserted into
the transmit data pattern when a Low-to-High transition occurs on the INSLER pin. Note that in
QRSS mode, logic error insertion is inhibited on a jammed bit (i.e. a bit forced to one to suppress
transmission of more than 14 consecutive zeros).
The transceiver treats data patterns the same way it treats data applied to TPOS/TNEG. Therefore,
the inserted logic error will follow the data flow path as defined by the active loopback mode
2.7.3.3
Logic Error Detection (QPD)
After pattern synchronization is detected in QRSS mode, subsequent logic errors are reported on
the QPD pin. If a logic error occurs, the QPD pin goes High for half an RCLK cycle. Note that in
Host mode, the precise relationship between QPD and RCLK depends on the value of the CLKE
pin. When CLKE is Low, QPD goes High while RCLK is High; when CLKE is High, QPD goes
High while RCLK is Low. To tally logic errors, connect an error counter to QPD. A continuous
High on this pin indicates loss of either the QRSS pattern lock or a LOS condition. “Quasi-Random
Signal Source (QRSS)” on page 24 provides additional details on QRSS pattern lock criteria.
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Datasheet
INTEL [ INTEL ]
