LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data and clock recovered
from the twisted-pair line loop back through the transmit circuits to TTIP and TRING without jitter
attenuation.
Figure 9. Dual Loopback
TTIP
TCLK
TPOS
TNEG
Timing &
Control
TRING
JA*
* If Enabled
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
2.7.2
Internal Pattern Generation and Detection
2.7.2.1
Transmit All Ones (TAOS)
See Figure 10. When TAOS is active, the transceiver ignores the TPOS and TNEG inputs and
transmits a continuous stream of 1’s at the TCLK frequency. When TCLK is not supplied, TAOS
timing is derived from MCLK. This can be used as the Alarm Indication Signal (AIS–also called
the Blue Alarm).
Both TAOS and LLOOP can operate simultaneously as shown in Figure 5, however, RLOOP
inhibits TAOS. When both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to
RCLK and RPOS/RNEG (through the jitter attenuator if enabled), and the all ones pattern is also
routed to TTIP/TRING.
In Host mode, TAOS is activated when bit CR2.ETAOS = 1. In Hardware mode, setting the TAOS
pin High activates TAOS.
Figure 10. TAOS Data Path
TAOS
TTIP
Timing &
Control
TCLK
TPOS
TNEG
TRING
* If Enabled
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
2.7.2.2
Quasi-Random Signal Source (QRSS)
See Figure 11. The Quasi-Random Signal Source (QRSS) is a 220-1 pseudo-random bit sequence
(PRBS) with no more than 14 consecutive zeros.
Both Hardware and Host Modes allow QRSS mode. The QRSS pattern is normally locked to
TCLK, however, if there is no TCLK, MCLK is the clock source. Bellcore Pub 62411 defines the
T1 QRSS transmit format.
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Datasheet
INTEL [ INTEL ]
