21150
2.2
Secondary PCI Bus Interface Signals
Table 5 describes the secondary PCI bus interface signals.
Table 5. Secondary PCI Bus Interface Signals (Sheet 1 of 3)
Signal Name
Type
Description
Secondary PCI interface address/data. These signals are a
multiplexed address and data bus. During theaddress phase
or phases of a transaction, the initiator drives a physical
address on s_ad<31:0>. During the data phases of a
transaction, the initiator drives write data, or the target drives
read data, on s_ad<31:0>. When the secondary PCI bus is
idle, the 21150 drives s_ad to a valid logic level when its
secondary bus grant is asserted.
s_ad<31:0>
TS
Secondary PCI interface command/byte enables. These
signals are a multiplexed command field and byte enable field.
During the address phase or phases of a transaction, the
initiator drives the transaction type on s_cbe_l<3:0>. When
there are two address phases, the first address phase carries
the dual address command and the second address phase
carries the transaction type. For both read and write
transactions, the initiator drives byte enables on s_cbe_l<3:0>
during the data phases. When the secondary PCI bus is idle,
the 21150 drives s_cbe_l to a valid logic level when its
secondary bus grant is asserted.
s_cbe_l<3:0>
TS
Secondary PCI interface parity. Signal s_par carries the even
parity of the 36 bits of s_ad<31:0> and s_cbe_l<3:0> for both
address and data phases. Signal s_par is driven by the same
agent that has driven the address (for address parity) or the
data (for data parity). Signal s_par contains valid parity one
cycle after the address is valid (indicated by assertion of
s_frame_l), or one cycle after data is valid (indicated by
assertion of s_irdy_l for write transactions and s_trdy_l for
read transactions). Signal s_par is driven by the device driving
read or write data one cycle after s_ad is driven. Signal s_par
is tristated one cycle after the s_ad lines are tristated. Devices
receiving data sample s_par as an input in order to check for
possible parity errors. When the secondary PCI bus is idle, the
21150 drives s_par to a valid logic level when its secondary
bus grant is asserted (one cycle after the s_ad bus is parked).
s_par
TS
Secondary PCI interface FRAME#. Signal s_frame_l is driven
by the initiator of a transaction to indicate the beginning and
duration of an access on the secondary PCI bus. Signal
s_frame_l assertion (falling edge) indicates the beginning of a
PCI transaction. While s_frame_l remains asserted, data
transfers can continue. The deassertion of s_frame_l indicates
the final data phase requested by the initiator. When the
secondary PCI bus is idle, s_frame_l is driven to a deasserted
state for one cycle and then is sustained by an external pull-up
resistor.
s_frame_l
STS
Preliminary Datasheet
11
INTEL [ INTEL ]
