21150
Table 4. Primary PCI Bus Interface Signals (Sheet 3 of 3)
Signal Name
Type
Description
Primary PCI interface PERR#. Signal p_perr_l is asserted
when a data parity error is detected for data received on the
primary interface. The timing of p_perr_l corresponds to p_par
driven one cycle earlier and p_ad and p_cbe_l driven two
cycles earlier. Signal p_perr_l is asserted by the target during
write transactions, and by the initiator during read
p_perr_l
STS
transactions. When the primary bus is idle, p_perr_l is driven
to a deasserted state for one cycle and then is sustained by an
external pull-up resistor.
Primary PCI interface SERR#. Signal p_serr_l can be driven
low by any device on the primary bus to indicate a system
error condition. The 21150 can assert p_serr_l for the following
reasons:
•
•
•
•
•
•
•
•
•
Address parity error
Posted write data parity error on target bus
Secondary bus s_serr_l assertion
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
p_serr_l
OD
Delayed transaction master timeout
Signal p_serr_l is pulled up through an external resistor.
Primary PCI bus REQ#. Signal p_req_l is asserted by the
21150 to indicate to the primary bus arbiter that it wants to
start a transaction on the primary bus. When the 21150
receives a target retry or disconnect in response to initiating a
transaction, the 21150 deasserts p_req_l for at least two PCI
clock cycles before asserting it again.
p_req_l
p_gnt_l
TS
Primary PCI bus GNT#. When asserted, p_gnt_lindicates to
the 21150 that access to the primary bus is granted. The
21150 can start a transaction on the primary bus when the bus
is idle and p_gnt_l is asserted. When the 21150 has not
requested use of the bus and p_gnt_l is asserted, the 21150
must drive p_ad, and p_par to valid logic levels.
I
10
Preliminary Datasheet
INTEL [ INTEL ]
