21150
Table 8. Clock Signals (Sheet 2 of 2)
Secondary interface PCI CLK. Provides timing for all
transactions on the secondary PCI bus. All secondary PCI
inputs are sampled on the rising edge of s_clk, and all
secondary PCI outputs are driven from the rising edge of
s_clk. Frequencies supported by the 21150 range from 0 MHz
to 33 MHz, or 0 MHz to 66 MHz for a 66 MHz capable 21150.
s_clk
I
Secondary interface PCI CLK outputs. Signals s_clk_o<9:0>
are 10 clock outputs generated from the primary interface
clock input, p_clk. These clocks operate at the same
frequency of p_clk, or at half the p_clk frequency when the
primary bus frequency is 66 MHz and the secondary bus
frequency is 33 MHz.
s_clk_o<9:0>
O
When these clocks are used, one of the clock outputs must be
fed back to the secondary clock input, s_clk. Unused clock
outputs can be disabled by using the serial disable mask
mechanism using the gpio pins and msk_in or by writing the
secondary clock disable bits in configuration space; otherwise,
terminate them electrically.
2.6
Reset Signals
Table 9 describes the reset signals.
Table 9. Reset Signals
Signal Name
Type
Description
Bus/power clock control management pin. When signal bpcce
is tied high, and when the 21150 is placed in the D3hot power
state, it enables the 21150 to place the secondary bus in the
B2 power state. The 21150 disables the secondary clocks and
drives them to 0. When tied low, placing the 21150 in the D3hot
power state has no effect on the secondary bus clocks.
bpcce1
p_rst_l
I
I
Primary PCI bus RST#. Signal p_rst_l forces the 21150 to a
known state. All register state is cleared, and all primary PCI
bus outputs are tristated. Signal p_rst_l is asynchronous to
p_clk.
Secondary PCI bus RST#. Signal s_rst_l is driven by the
21150 and acts as the PCI reset for the secondary bus. The
21150 asserts s_rst_l when any of the following conditions is
met:
•
•
Signal p_rst_l is asserted.
The secondary reset bit in the bridge control register in
configuration space is set.
•
The chip reset bit in the diagnostic control register in
configuration space is set.
s_rst_l
O
When the 21150 asserts s_rst_l, it tristates all secondary
control signals and drives zeros on s_ad, s_cbe_l, and s_par.
Signal s_rst_l remains asserted until p_rst_l is deasserted, the
gpio serial clock mask has been shifted in, and the secondary
reset bit is clear. Assertion of s_rst_l by itself does not clear
register state, and configuration registers are still accessible
from the primary PCI interface.
1. For 21150-AB and later revisions only
Preliminary Datasheet
15
INTEL [ INTEL ]
