21150
2.1
Primary PCI Bus Interface Signals
Table 4 describes the primary PCI bus interface signals.
Table 4. Primary PCI Bus Interface Signals (Sheet 1 of 3)
Signal Name
Type
Description
Primary PCI interface address/data. These signals are a
multiplexed address and data bus. During the address phase
or phases of a transaction, the initiator drives a physical
address on p_ad<31:0>. During the data phases of a
transaction, the initiator drives write data, or the target drives
read data, on p_ad<31:0>. When the primary PCI bus is idle,
the 21150 drives p_ad to a valid logic level when p_gnt_l is
asserted.
p_ad<31:0>
TS
Primary PCI interface command/byte enables. These signals
are a multiplexed command field and byte enable field. During
the address phase or phases of a transaction, the initiator
drives the transaction type on p_cbe_l<3:0>. When there are
two address phases, the first address phase carries the dual
address command and the second address phase carries the
transaction type. For both read and write transactions, the
initiator drives byte enables on p_cbe_l<3:0> during the data
phases. When the primary PCI bus is idle, the 21150 drives
p_cbe_l to a valid logic level when p_gnt_l is asserted.
p_cbe_l<3:0>
TS
Primary PCI interface parity. Signal p_par carries the even
parity of the 36 bits of p_ad<31:0> and p_cbe_l<3:0> for both
address and data phases. Signal p_par is driven by the same
agent that has driven the address (for address parity) or the
data (for data parity). Signal p_par contains valid parity one
cycle after the address is valid (indicated by assertion of
p_frame_l, or one cycle after data is valid (indicated by
assertion of p_irdy_l for write transactions and p_trdy_l for
read transactions). Signal p_par is driven by the device driving
read or write data one cycle after p_ad is driven. Signal p_par
is tristated one cycle after the p_ad lines are tristated. Devices
receiving data sample p_par as an input to check for possible
parity errors. When the primary PCI bus is idle, the 21150
drives p_par to a valid logic level when p_gnt_l is asserted
(one cycle after the p_ad bus is parked).
p_par
TS
Primary PCI interface FRAME#. Signal p_frame_l is driven by
the initiator of a transaction to indicate the beginning and
duration of an access on the primary PCI bus. Signal
p_frame_l assertion (falling edge) indicates the beginning of a
PCI transaction. While p_frame_l remains asserted, data
transfers can continue. The deassertion of p_frame_l indicates
the final data phase requested by the initiator. When the
primary PCI bus is idle, p_frame_l is driven to a deasserted
state for one cycle and then is sustained by an external pull-up
resistor.
p_frame_l
STS
Primary PCI interface IRDY#. Signal p_irdy_l is driven by the
initiator of a transaction to indicate the initiator’s ability to
complete the current data phase on the primary PCI bus.
During a write transaction, assertion of p_irdy_l indicates that
valid write data is being driven on the p_ad bus. During a read
transaction, assertion of p_irdy_l indicates that the initiator is
able to accept read data for the current data phase. Once
asserted during a given data phase, p_irdy_l is not deasserted
until the data phase completes. When the primary bus is idle,
p_irdy_l is driven to a deasserted state for one cycle and then
is sustained by an external pull-up resistor.
p_irdy_l
STS
8
Preliminary Datasheet
INTEL [ INTEL ]
