21150
Table 4. Primary PCI Bus Interface Signals (Sheet 2 of 3)
Signal Name
Type
Description
Primary PCI interface TRDY#. Signal p_trdy_l is driven by the
target of a transaction to indicate the target’s ability to
complete the current data phase on the primary PCI bus.
During a write transaction, assertion of p_trdy_l indicates that
the target is able to accept write data for the current data
phase. During a read transaction, assertion of p_trdy_l
indicates that the target is driving valid read data on the p_ad
bus. Once asserted during a given data phase, p_trdy_l is not
deasserted until the data phase completes. When the primary
bus is idle, p_trdy_l is driven to a deasserted state for one
cycle and then is sustained by an external pull-up resistor.
p_trdy_l
STS
Primary PCI interface DEVSEL#. p_devsel_l is asserted by the
target, indicating that the device is accepting the transaction.
As a target, the 21150 performs positive decoding on the
address of a transaction initiated on the primary bus to
determine whether to assert p_devsel_l. As an initiator of a
transaction on the primary bus, the 21150 looks for the
assertion of p_devsel_l within five cycles of p_frame_l
assertion; otherwise, the 21150 terminates the transaction with
a master abort. When the primary bus is idle, p_devsel_l is
driven to a deasserted state for one cycle and then is
sustained by an external pull-up resistor.
p_devsel_l
STS
Primary PCI interface STOP#. Signal p_stop_l is driven by the
target of the current transaction, indicating that the target is
requesting the initiator to stop the current transaction on the
primary bus.
•
When p_stop_l is asserted in conjunction with p_trdy_l
and p_devsel_l assertion, a disconnect with data transfer
is being signaled.
•
When p_stop_l and p_devsel_l are asserted, but p_trdy_l
is deasserted, a target disconnect without data transfer is
being signaled. When this occurs on the first data phase,
that is, no data is transferred during the transaction, this is
referred to as a target retry.
p_stop_l
STS
•
When p_stop_l is asserted and p_devsel_l is deasserted,
the target is signaling a target abort.
When the primary bus is idle, p_stop_l is driven to a
deasserted state for one cycle and then is sustained by an
external pull-up resistor.
Primary PCI interface LOCK#. Signal p_lock_l is deasserted
during the first address phase of a transaction and is asserted
one clock cycle later by an initiator attempting to perform an
atomic operation that may take more than one PCI transaction
to complete. The 21150 samples p_lock_l as a target and can
propagate the lock across to the secondary bus. The 21150
does not drive p_lock_l as an initiator; that is, the 21150 does
not propagate locked transactions upstream. When released
by an initiator, p_lock_l is driven to a deasserted state for one
cycle and then is sustained by an external pull-up resistor.
p_lock_l
p_idsel
I
I
Primary PCI interface IDSEL#. Signal p_idsel is used as the
chip select line for Type 0 configuration accesses to 21150
configuration space. When p_idsel is asserted during the
address phase of a Type 0 configuration transaction, the
21150 responds to the transaction by asserting p_devsel_l.
Preliminary Datasheet
9
INTEL [ INTEL ]
