21150
1.3
Posted Write Queue
The posted write queue contains the address and data of memory write transactions targeted for the
opposite interface. The posted write transaction can consist of an arbitrary number of data phases,
subject to the amount of space in the queue and disconnect boundaries. The posted write queue can
contain multiple posted write transactions. The number of posted write transactions that can be
queued at one time is dependent upon their burst size. The posted write queue consists of 88 bytes
in each direction.
1.4
Delayed Transaction Queue
For a delayed write request transaction, the delayed transaction queue contains the address, bus
command, 1 Dword of write data, byte enable bits, and parity. When the delayed write transaction
is completed on the target bus, the write completion status is added to the corresponding entry.
For a delayed read request transaction, the delayed transaction queue contains the address and bus
command, and for nonprefetchable read transactions, the byte enable bits. When the delayed read
transaction is completed on the target bus, the read completion status corresponding to that
transaction is added to the delayed request entry. Read data is placed in the read data queue.
The delayed transaction queue can hold up to three transactions (any combination of read and write
transactions).
1.5
Read Data Queue
The read data queue contains read data transferred from the target during a delayed read
completion. Read data travels in the opposite direction of the transaction. The primary-to-
secondary read data queue contains read data corresponding to a delayed read transaction residing
in the secondary-to-primary delayed transaction queue. The secondary-to-primary read data queue
contains read data corresponding to a delayed read transaction in the primary-to-secondary delayed
transaction queue. The amount of read data per transaction depends on the amount of space in the
queue and disconnect boundaries.
Read data for up to three transactions, subject to the burst size of the read transactions and available
queue space, can be stored. The read data queue for the 21150 consists of 72 bytes in each
direction.
6
Preliminary Datasheet
INTEL [ INTEL ]
