21150
Table 1. 21150 Functional Blocks (Sheet 2 of 2)
Data path for data received on the secondary interface and
driven on the primary interface. This block is used for write
transactions initiated on the secondary PCI bus and for
returning read data for read transactions initiated on the
primary PCI bus. This block contains logic to store and, for
posted write transactions, to increment the address of the
current transaction. This block also performs bus
Secondary-to-Primary Data Path
command and configuration address format translations
Configuration space registers and corresponding control
logic. These registers are accessible from the primary
interface only.
Configuration Registers
Logic for secondary bus arbitration. This block receives
s_req_l<8:0>, as well as the 21150 secondary bus request,
and drives one of the s_gnt_l<8:0> lines or the 21150
secondary bus grant.
Secondary Bus Arbiter Control
1.2
Data Path
The data path consists of a primary-to-secondary data path for transactions and data flowing in the
downstream direction and a secondary-to-primary data path for transactions and data flowing in the
upstream direction.
Both data paths have the following queues:
• Posted write queue
• Delayed transaction queue
• Read data queue
To prevent deadlocks and to maintain data coherency, a set of ordering rules is imposed on the
forwarding of posted and delayed transactions across the 21150. The queue structure, along with
the order in which the transactions in the queues are initiated and completed, supports these
ordering requirements. Section 6.0 describes the 21150 ordering rules in detail.
See Section 4.0 for a detailed description of 21150 PCI bus operation.
Figure 4 shows the 21150 data path for the downstream direction, and the following sections
describe the data path queues.
Figure 4. 21150 Downstream Data Path
Delayed
Transaction
Queue
Address
Control
s_ad
Posted Write Data Queue
Delayed Read Data Queue
LJ-04634.AI4
Preliminary Datasheet
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INTEL [ INTEL ]
