M10-DATASHEET
2015.05.04
56
JTAG Timing Parameters
JTAG Timing Parameters
Table 46: JTAG Timing Parameters for MAX 10 Devices—Preliminary
The values are based on CL = 10 pF of TDO .
The affected Boundary Scan Test (BST) instructions are SAMPLE/PRELOAD, EXTEST, INTEST, and CHECK_STATUS.
Non-BST and non-CONFIG_IO Operation
BST and CONFIG_IO Operation
Symbol
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
tJCP
TCK clock period
40
20
20
2
—
—
—
—
—
—
50
25
25
2
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tJCH
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port setup time
JTAG port hold time
tJCL
tJPSU_TDI
tJPSU_TMS
tJPH
3
3
10
—
10
—
tJPCO
JTAG port clock to
output
•
•
15 (for VCCIO = 3.3,
3.0, and 2.5 V)
17 (for VCCIO = 1.8
and 1.5 V)
•
•
18 (for VCCIO = 3.3,
3.0, and 2.5 V)
20 (for VCCIO = 1.8
and 1.5 V)
tJPZX
JTAG port high
impedance to valid
output
—
—
—
—
ns
ns
•
•
15 (for VCCIO = 3.3,
3.0, and 2.5 V)
17 (for VCCIO = 1.8
and 1.5 V)
•
•
15 (for VCCIO = 3.3,
3.0, and 2.5 V)
17 (for VCCIO = 1.8
and 1.5 V)
tJPXZ
JTAG port valid output
to high impedance
•
•
15 (for VCCIO = 3.3,
3.0, and 2.5 V)
17 (for VCCIO = 1.8
and 1.5 V)
•
•
15 (for VCCIO = 3.3,
3.0, and 2.5 V)
17 (for VCCIO = 1.8
and 1.5 V)
MAX 10 FPGA Device Datasheet
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