M10-DATASHEET
2015.05.04
35
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
–I6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
Typ
Max
Min
Max
Min
Max
tLOCK
Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
—
—
—
1
—
1
—
1
ms
configuration
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Table 36: True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary
True RSDS transmitter is only supported at bottom I/O banks. Emulated RSDS transmitter is supported at the output pin of all I/O banks.
–I6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
5
Typ
—
—
—
—
—
—
Max
155
155
155
155
155
310
Min
5
Max
155
155
155
155
155
310
Min
5
Max
155
155
155
155
155
310
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
5
5
—
5
—
Input clock
5
5
—
5
—
frequency (high-
speed I/O
fHSCLK
5
5
—
5
—
performance pin)
5
5
—
5
—
5
5
—
5
—
MAX 10 FPGA Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
