M10-DATASHEET
2015.05.04
37
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
–I6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
Typ
Max
Min
Max
Min
Max
TCCS(52) Transmitter
—
—
—
410
—
410
—
410
ps
channel-to-channel
skew
Output jitter (high-
speed I/O
—
—
—
—
—
—
425
470
—
—
—
—
425
470
—
—
—
—
425
470
ps
ps
performance pin)
(53)
tx Jitter
Output jitter (low-
speed I/O
performance pin)
tRISE
Rise time
Fall time
20 – 80%,
—
—
—
500
500
—
—
—
1
—
—
—
500
500
—
—
—
1
—
—
—
500
500
—
—
—
1
ps
ps
CLOAD = 5 pF
tFALL
tLOCK
20 – 80%,
CLOAD = 5 pF
Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
—
ms
configuration
(52)
(53)
TCCS specifications apply to I/O banks from the same side only.
TX jitter is the jitter induced from core noise and I/O switching noise.
MAX 10 FPGA Device Datasheet
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