M10-DATASHEET
2015.05.04
33
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
Table 35: True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary
True PPDS transmitter is only supported at bottom I/O banks. Emulated PPDS transmitter is supported at the output pin of all I/O banks.
–I6, –C7, –I7
–A7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–C8
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Symbol
Parameter
Mode
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155
155
155
155
155
310
310
310
310
310
310
310
150
150
150
150
150
300
Min
5
Max
155
155
155
155
155
310
310
310
310
310
310
310
150
150
150
150
150
300
Min
5
Max
155
155
155
155
155
310
310
310
310
310
310
310
150
150
150
150
150
300
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
5
5
5
Input clock
5
5
5
frequency (high-
speed I/O
fHSCLK
5
5
5
performance pin)
5
5
5
5
5
5
100
80
70
40
20
10
5
100
80
70
40
20
10
5
100
80
70
40
20
10
5
Data rate (high-
HSIODR speed I/O
performance pin)
5
5
5
Input clock
5
5
5
frequency (low-
speed I/O
fHSCLK
5
5
5
performance pin)
5
5
5
5
5
5
MAX 10 FPGA Device Datasheet
Send Feedback
Altera Corporation