M10-DATASHEET
2015.05.04
34
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
–I6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Symbol
Parameter
Mode
Unit
Min
100
80
Typ
—
—
—
—
—
—
—
Max
300
300
300
300
300
300
55
Min
100
80
Max
300
300
300
300
300
300
55
Min
100
80
Max
300
300
300
300
300
300
55
×10
×8
×7
×4
×2
×1
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
—
—
Data rate (low-
70
70
—
70
—
HSIODR speed I/O
40
40
—
40
—
performance pin)
20
20
—
20
—
10
10
—
10
—
tDUTY
Duty cycle on
transmitter output
clock
45
45
—
45
—
TCCS(50) Transmitter
—
—
—
—
—
—
—
—
—
410
425
470
—
—
—
—
—
—
410
425
470
—
—
—
—
—
—
410
425
470
ps
ps
ps
channel-to-channel
skew
Output jitter (high-
speed I/O
performance pin)
(51)
tx Jitter
Output jitter (low-
speed I/O
performance pin)
tRISE
Rise time
20 – 80%,
—
—
500
500
—
—
—
—
500
500
—
—
—
—
500
500
—
—
ps
ps
CLOAD = 5 pF
tFALL
Fall time
20 – 80%,
CLOAD = 5 pF
(50)
TCCS specifications apply to I/O banks from the same side only.
TX jitter is the jitter induced from core noise and I/O switching noise.
(51)
MAX 10 FPGA Device Datasheet
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