M10-DATASHEET
2015.05.04
38
Emulated RSDS_E_1R Transmitter Timing Specifications
Emulated RSDS_E_1R Transmitter Timing Specifications
Table 37: Emulated RSDS_E_1R Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary
Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
–I6, –C7, –I7
–A7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–C8
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Symbol
Parameter
Mode
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
85
Min
5
Max
85
Min
5
Max
85
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
5
85
5
85
5
85
Input clock
5
85
5
85
5
85
frequency (high-
speed I/O
fHSCLK
5
85
5
85
5
85
performance pin)
5
85
5
85
5
85
5
170
170
170
170
170
170
170
85
5
170
170
170
170
170
170
170
85
5
170
170
170
170
170
170
170
85
100
80
70
40
20
10
5
100
80
70
40
20
10
5
100
80
70
40
20
10
5
Data rate (high-
HSIODR speed I/O
performance pin)
5
85
5
85
5
85
Input clock
5
85
5
85
5
85
frequency (low-
speed I/O
fHSCLK
5
85
5
85
5
85
performance pin)
5
85
5
85
5
85
5
170
5
170
5
170
MAX 10 FPGA Device Datasheet
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