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10M08SCU169I7G 参数 Datasheet PDF下载

10M08SCU169I7G图片预览
型号: 10M08SCU169I7G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 8000-Cell, CMOS, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169]
分类和应用: 可编程逻辑
文件页数/大小: 68 页 / 976 K
品牌: INTEL [ INTEL ]
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M10-DATASHEET  
2015.05.04  
31  
Dual Supply Devices ADC Performance Specifications  
Parameter  
Symbol  
Condition  
Min  
–0.2  
–0.5  
–0.5  
–0.75  
–0.9  
Typ  
Max  
0.2  
Unit  
%FS  
%FS  
%FS  
%FS  
LSB  
Prescalar disabled  
Prescalar enabled  
Prescalar disabled  
Prescalar enabled  
Offset error and drift  
Eoffset  
0.5  
0.5  
Gain error and drift  
Egain  
DNL  
0.75  
0.9  
DC Accuracy  
External VREF, no  
missing code  
Differential non linearity  
Internal VREF, no  
missing code  
–1  
1.7  
LSB  
Integral non linearity  
INL  
–2  
–70 (42)(43)  
2
LSB  
dB  
Total harmonic distortion  
THD  
FIN = 50 kHz, FS = 1  
MHz, PLL  
Signal-to-noise ratio  
SNR  
FIN = 50 kHz, FS = 1  
MHz, PLL  
62 (44)(45)  
dB  
dB  
AC Accuracy  
Signal-to-noise and distortion  
SINAD  
FIN = 50 kHz, FS = 1  
MHz, PLL  
61.5 (46)(47)  
(42)  
(43)  
(44)  
(45)  
(46)  
(47)  
Total harmonic distortion is –65 dB for dual function pin.  
THD with prescalar enabled is 6dB less than the specification.  
Signal-to-noise ratio is 54 dB for dual function pin.  
SNR with prescalar enabled is 6dB less than the specification.  
Signal-to-noise and distortion is 53 dB for dual function pin.  
SINAD with prescalar enabled is 6dB less than the specification.  
MAX 10 FPGA Device Datasheet  
Send Feedback  
Altera Corporation  
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