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10M08SCU169I7G 参数 Datasheet PDF下载

10M08SCU169I7G图片预览
型号: 10M08SCU169I7G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 8000-Cell, CMOS, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169]
分类和应用: 可编程逻辑
文件页数/大小: 68 页 / 976 K
品牌: INTEL [ INTEL ]
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M10-DATASHEET  
2015.05.04  
29  
Single Supply Devices ADC Performance Specifications  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
Unit  
Total harmonic distortion  
THD  
FIN = 50 kHz, FS = 1  
MHz, PLL  
–65 (35)  
dB  
Signal-to-noise ratio  
SNR  
FIN = 50 kHz, FS = 1  
MHz, PLL  
54 (36)  
53 (37)  
dB  
dB  
AC Accuracy  
Signal-to-noise and distortion  
SINAD  
FIN = 50 kHz, FS = 1  
MHz, PLL  
Temperature sampling rate  
Absolute accuracy  
TS  
50  
10  
kSPS  
°C  
–40 to 125°C,  
On-Chip Tempera‐  
ture Sensor  
with 64 samples  
averaging  
(38)  
Single measurement  
1
1
Cycle  
Cycle  
Continuous  
Conversion Rate (39) Conversion time  
measurement  
Temperature  
measurement  
1
Cycle  
Related Information  
Guidelines: Board Design for Analog Input, MAX 10 Analog-to-Digital Converter User Guide  
Provides more information about the conversion rate and RC equation.  
(35)  
(36)  
(37)  
(38)  
THD with prescalar enabled is 6dB less than the specification.  
SNR with prescalar enabled is 6dB less than the specification.  
SINAD with prescalar enabled is 6dB less than the specification.  
For the Quartus II software version 15.0 and later, Altera Modular ADC and Altera Modular Dual ADC IP cores handle the 64 samples averaging.  
For the Quartus II software versions prior to 14.1, you need to implement your own averaging calculation.  
(39)  
For more detailed description, refer to Timing section in the MAX 10 Analog-to-Digital Converter User Guide.  
MAX 10 FPGA Device Datasheet  
Send Feedback  
Altera Corporation  
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