A10-DATASHEET
2015.12.31
104
Document Revision History
Date
Version
Changes
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Added –I1S, –I2S, and –E2S speed grades to the following tables:
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Clock Tree Performance for Arria 10 Devices
DSP Block Performance Specifications for Arria 10 Devices
Memory Block Performance Specifications for Arria 10 Devices
High-Speed I/O Specifications for Arria 10 Devices
Memory Output Clock Jitter Specifications for Arria 10 Devices
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Updated fIN minimum value from 27 MHz to 50 MHz for all speed grades in the Fractional PLL Specifica‐
tions for Arria 10 Devices table.
Changed the description for fINPFD to "Input clock frequency to the PFD" in the I/O PLL Specifications for
Arria 10 Devices table.
Updated DSP Block Performance Specifications for Arria 10 Devices table for VCC and VCCP at 0.9 V typical
value. Added DSP specifications for VCC and VCCP at 0.95 V typical value.
Updated Ibias minimum value from 8 μA to 10 μA and maximum value from 200 μA to 100 μA in the
External Temperature Sensing Diode Specifications for Arria 10 Devices table.
Added DPA (soft CDR mode) specifications in High-Speed I/O Specifications for Arria 10 Devices table.
Added description in POR Specifications section: Power-on reset (POR) delay is defined as the delay
between the time when all the power supplies monitored by the POR circuitry reach the minimum
recommended operating voltage to the time when the nSTATUSis released high and your device is ready to
begin configuration.
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Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades
in Arria 10 Devices chapter.
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FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
AS Configuration Timing Waveform
PS Configuration Timing Waveform
Removed the DCLK-to-DATA[] ratio when both encryption and compression are turned on. Added
description to the table: You cannot turn on encryption and compression at the same time for Arria 10
devices.
Arria 10 Device Datasheet
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