A10-DATASHEET
2015.12.31
101
Document Revision History
Date
Version
Changes
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Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria 10 Devices table.
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Changed Tclk to Tsdmmc_clk_out and TMMC_CLKto TSDMMC_CLK_OUT.
Updated Td min from 5.5 ns to 8.5 ns and max from 12.5 ns to 11.5 ns.
Updated note to Td.
Changed the title and symbols in the following timing diagrams:
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Changed from "NAND Data Input Cycle Timing Diagram" to "NAND Data Output Cycle Timing
Diagram". Changed from DIN to DOUT
Changed from "NAND Data Output Cycle Timing Diagram" to "NAND Data Input Cycle Timing
Diagram". Changed from DOUT to DIN.
Changed from "NAND Extended Data Output (EDO) Cycle Timing Diagram" to "NAND Data Input
Timing Diagram for Extended Data Output (EDO) Cycle". Changed from DOUT to DIN.
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Changed from "ARM Trace Timing Characteristics" to "Trace Timing Characteristics".
Updated the description in the GPIO Interface topic.
Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Arria 10 Devices table.
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Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs.
Updated fMAX for FPP ×8/×16 from 125 MHz to 100 MHz.
Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
Updated the minimum value for tST2CK from 2 μs to 10 μs.
Updated the maximum value for tCD2UM from 437 μs to 830 μs.
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Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Arria 10 Devices table.
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Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs.
Updated fMAX for FPP ×8/×16 from 125 MHz to 100 MHz.
Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
Updated the minimum value for tST2CK from 2 μs to 10 μs.
Updated the maximum value for tCD2UM from 437 μs to 830 μs.
Updated maximum value for tCD2UM from 437 μs to 830 μs in AS Timing Parameters for AS ×1 and AS ×4
Configurations in Arria 10 Devices table.
Arria 10 Device Datasheet
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