A10-DATASHEET
2015.12.31
66
SD/MMC Timing Characteristics
SD/MMC Timing Characteristics
Table 62: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria 10 Devices—Preliminary
These timings apply to SD, MMC, and embedded MMC cards operating at 1.8 V and 3.3 V.
Symbol
Description
Min
Typ
Max
Unit
SDMMC_CLK_OUT clock period (Identification
mode)
—
2500
—
ns
Tsdmmc_clk_
out
SDMMC_CLK_OUT clock period (Standard SD
mode)
—
—
40
20
—
—
ns
ns
SDMMC_CLK_OUT clock period (High speed SD
mode)
Tdutycycle
Tsu
SDMMC_CLK_OUT duty cycle
45
4.0
1.0
8.5
50
—
—
—
55
—
%
ns
ns
ns
SDMMC_CMD/SDMMC_D[7:0] input setup (86)
SDMMC_CMD/SDMMC_D[7:0] input hold (87)
SDMMC_CMD/SDMMC_D[7:0] output delay (88)
Th
—
Td
11.5
(86)
(87)
(88)
These values assume the use of the phase shift implemented in the Boot ROM using smplsel= 0 and TSDMMC_CLK_OUT= 50 MHz (20 ns) in this
equation: 4 – (TSDMMC_CLK_OUT× smpl_sel/ 8) ns. The smplselfield is in the sdmmcregister in the System Manager module.
These values assume the use of the phase shift implemented in the Boot ROM using smplsel= 0 and TSDMMC_CLK_OUT= 50 MHz (20 ns) in this
equation: 1 + (TSDMMC_CLK_OUT× smpl_sel/ 8) ns. The smplselfield is in the sdmmcregister in the System Manager module.
These values assume the use of the phase shift implemented in the Boot ROM using drvsel= 3 and TSDMMC_CLK_OUT= 50 MHz (20 ns) in the
following equations:
•
•
For min value: (TSDMMC_CLK_OUT× drv_sel/ 8) + 1 ns
For max value: (TSDMMC_CLK_OUT× drv_sel/ 8) + 4 ns
The drvselfield is in the sdmmcregister in the System Manager module. You must not set drvselto 0 because this does not provide the necessary
delay to meet the hold time of the flash device.
Arria 10 Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
