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10AS066K4F40E3SG 参数 Datasheet PDF下载

10AS066K4F40E3SG图片预览
型号: 10AS066K4F40E3SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
70  
Ethernet Media Access Controller (EMAC) Timing Characteristics  
Table 67: RMII TX Timing Requirements for Arria 10 Devices—Preliminary  
Symbol  
Description  
Min  
Typ  
Max  
Unit  
Td  
TX_CLK to TXD/TX_CTL output data delay  
0.45  
4
ns  
Table 68: RMII RX Timing Requirements for Arria 10 Devices—Preliminary  
Symbol  
Description  
Min  
1
Typ  
Max  
Unit  
ns  
Tsu  
Th  
RX_D/RX_CTL setup time  
RX_D/RX_CTL hold time  
0.4  
ns  
Table 69: Management Data Input/Output (MDIO) Timing Requirements for Arria 10 Devices—Preliminary  
Symbol  
Description  
Min  
Typ  
400  
Max  
Unit  
Tclk  
MDC clock period  
ns  
ns  
ns  
ns  
Td  
Tsu  
Th  
MDC to MDIO output data delay  
Setup time for MDIO data  
Hold time for MDIO data  
10.2  
10  
20  
10  
Figure 16: MDIO Timing Diagram  
MDC  
Td  
MDIO_OUT  
Dout0  
Dout1  
TSU  
Th  
Din0  
MDIO_IN  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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