A10-DATASHEET
2015.12.31
69
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 65: RGMII RX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
—
—
—
1
Typ
8
Max
—
Unit
ns
Tclk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tsu
RX_CLK clock period
RX_CLK clock period
RX_CLK clock period
40
400
—
—
ns
—
ns
RX_D/RX_CTL setup time
RX_D/RX_CTL hold time
—
ns
Th
2.5
—
—
ns
Figure 15: RGMII RX Timing Diagram
RX_CLK
TSU
Th
RX_D[3:0]
RX_CTL
D0
D1
Table 66: Reduced Media Independent Interface (RMII) Clock Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Tclk (100Base-T)
Tclk (10Base-T)
Tdutycycle
Description
Min
—
Typ
20
Max
—
Unit
ns
ns
%
TX_CLK clock period
TX_CLK clock period
—
20
—
Clock duty cycle, internal clock source
Clock duty cycle, external clock source
45
35
50
55
Tdutycycle
50
65
%
Arria 10 Device Datasheet
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