A10-DATASHEET
2015.12.31
63
SPI Timing Characteristics
Symbol
Description
Min
–0.6
1
Typ
—
—
—
—
—
Max
1.4
4
Unit
(83)
Tdsslst
Tdio
Last SPI_CLK edge to SPI_SS deasserted
Master-out slave-in (MOSI) output delay
Input setup in respect to SPI_CLK capture edge
Input hold in respect to SPI_CLK capture edge
ns
ns
(84)
Tsu
Th
2
—
ns
(84)
0
—
ns
Tdssb2b
Minimum delay of slave select deassertion
between two back-to-back transfers (frames)
1
—
SPI_CLK
Figure 8: SPI Master Output Timing Diagram
Tdssfrst (max)
Tdssfrst (min)
SPI_SS
SPI_CLK
SPI_MOSI
SPI_MISO
OUT0
OUT1
OUTn
Tdsslst (min)
Tdsslst (max)
Tdio (min)
Tdio (max)
(84)
The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the
scpolregister bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
Arria 10 Device Datasheet
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