A10-DATASHEET
2015.12.31
68
Ethernet Media Access Controller (EMAC) Timing Characteristics
Figure 13: USB ULPI Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
TSU Th
USB_DIR and USB_NXT
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 64: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Tclk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tdutycycle
Description
Min
—
Typ
8
Max
—
Unit
ns
TX_CLK clock period
TX_CLK clock period
TX_CLK clock period
TX_CLK duty cycle
—
40
400
50
—
—
ns
—
—
ns
45
55
%
Td
TX_CLK to TXD/TX_CTL output data delay
–0.5
0.5
ns
Figure 14: RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
D0
D1
Td
TX_CTL
Arria 10 Device Datasheet
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