A10-DATASHEET
2015.12.31
64
SPI Timing Characteristics
Figure 9: SPI Master Input Timing Diagram
SPI_SS
SPI_CLK
SPI_MOSI
SPI_MISO
IN0
IN1
INn
Tsu Th
Table 61: SPI Slave Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Tclk
Description
Min
20
45
5
Typ
—
50
—
—
—
—
—
—
—
Max
—
55
—
—
—
—
—
—
4
Unit
ns
%
SPI_CLK clock period
SPI_CLK duty cycle
Tdutycycle
Ts
SPI slave input setup time
ns
ns
ns
ns
ns
ns
ns
Th
SPI slave input hold time
5
Tssfsu
Tssfh
Tsslsu
Tsslh
Td
SPI_SS asserted to first active SPI_CLK edge setup (85)
SPI_SS asserted to first active SPI_CLK edge hold (85)
SPI_SS deasserted to last active SPI_CLK edge setup (85)
SPI_SS deasserted to last active SPI_CLK edge hold (85)
Master-in slave-out (MISO) output delay
5
5
5
5
1
(85)
The active edge differs depending on the operational mode. For Motorola SPI, the active edge can be the rising or falling edge depending on the
scpolregister bit; for TI SSP, the active edge is the falling edge; for Microwire, the active edge is the rising edge.
Arria 10 Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
