A10-DATASHEET
2015.12.31
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SPI Timing Characteristics
Figure 6: Quad SPI Flash Serial Output Timing Diagram
Tdio (min)
Tdssfrst
Tdsslst
Tdio (max)
QSPI_SS
SCLK_OUT
QSPI_DATA
OUT0
OUT1
OUTn
Figure 7: Quad SPI Flash Serial Input Timing Diagram
QSPI_SS
SCLK_OUT
Tdin_start
QSPI_DATA
IN0
IN1
INn
Tdin_end
SPI Timing Characteristics
Table 60: SPI Master Timing Requirements for Arria 10 Devices—Preliminary
You can adjust the input delay timing using the rx_sample_dlyregister.
Symbol
Description
Min
16.67
45
Typ
—
Max
—
Unit
ns
Tclk
Tdutycycle
SPI_CLK clock period
SPI_CLK duty cycle
50
55
%
(83)
Tdssfrst
SPI_SS asserted to first SPI_CLK edge
1.5
—
3.5
ns
(83)
SPI_SS behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
Arria 10 Device Datasheet
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