A10-DATASHEET
2015.12.31
61
HPS PLL Output Specifications
HPS PLL Output Specifications
The maximum HPS PLL lock time is 10 μs for all speed grades.
Quad SPI Flash Timing Characteristics
Table 59: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria 10 Devices—Preliminary
The input parameters are still pending characterization. Note that the Arria 10 HPS boot loader calibrates the input timing automatically.
Symbol
Tqspi_clk
Tclk
Description
Min
2.5
10
45
0.5
–2
1
Typ
—
—
50
—
—
—
—
Max
—
—
55
3
Unit
ns
ns
%
QSPI_CLK clock period (internal reference clock)
SCLK_OUT clock period (external clock)
SCLK_OUT duty cycle
Tdutycycle
(81)
Tdssfrst
QSPI_SS asserted to first SCLK_OUT edge
Last SCLK_OUT edge to QSPI_SS deasserted
QSPI_DATA output delay
ns
ns
ns
ns
(81)
Tdsslst
0.5
3
Tdo
Tdin_start
Valid input data start from falling clock edge
—
[(2 + Rdelay) ×
Tqspi_clk] – 4
Tdin_end
Valid input data end from falling clock edge
[(2 + Rdelay) ×
Tqspi_clk] + 2.2
—
—
—
ns
(82)
Tdssb2b
Minimum delay of slave select deassertion between
two back-to-back transfer
1
—
SCLK_OUT
(81)
(82)
You can increase this delay using the delay register in the Quad SPI module.
This delay is programmable in whole QSPI_CLK increments using the delay register in the Quad SPI module.
Arria 10 Device Datasheet
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