A10-DATASHEET
2015.12.31
38
I/O PLL Specifications
Symbol
Parameter
Condition
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
Min
—
Typ
—
Max
TBD
TBD
—
Unit
ps (p-p)
mUI (p-p)
bit
Cycle-to-cycle jitter for clock output
in integer mode
(55)
tOUTCCJ
dKBIT
—
—
Bit number of Delta Sigma Modulator
(DSM)
—
32
Related Information
Memory Output Clock Jitter Specifications on page 58
Provides more information about the external memory interface clock output jitter specifications.
I/O PLL Specifications
Table 38: I/O PLL Specifications for Arria 10 Devices—Preliminary
Symbol
Parameter
Condition
–1 speed grade
–2 speed grade
–3 speed grade
—
Min
10
Typ
—
—
—
—
—
—
—
—
—
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
800 (56)
700 (56)
650 (56)
325
fIN
Input clock frequency
10
10
fINPFD
Input clock frequency to the PFD
PLL VCO operating range
10
–1 speed grade
–2 speed grade
–3 speed grade
—
600
600
600
0.1
40
1600
1434
1250
8
fVCO
fCLBW
PLL closed-loop bandwidth
tEINDUTY
Input clock or external feedback clock
input duty cycle
—
60
fOUT
Output frequency for internal global or
–1, –2, –3 speed
grade
—
—
644
MHz
regional clock (Ccounter)
(56)
This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
Arria 10 Device Datasheet
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