A10-DATASHEET
2015.12.31
37
Fractional PLL Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fOUT
Output frequency for internal global
or regional clock
—
—
—
644
MHz
fDYCONFIGCLK Dynamic configuration clock for
—
—
—
—
—
—
100
1
MHz
ms
reconfig_clk
tLOCK
Time required to lock from end-of-
device configuration or deassertion of
pll_powerdown
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
—
—
—
1
ms
fCLBW
PLL closed-loop bandwidth
Accuracy of PLL phase shift
—
—
—
—
—
10
TBD
—
—
50
—
MHz
ps
tPLL_PSERR
tARESET
Minimum pulse width on the pll_
powerdownsignal
—
ns
FREF ≥ 100 MHz
FREF < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
UI (p-p)
ps (p-p)
(53)(54)
tINCCJ
Input clock cycle-to-cycle jitter
ps (p-p)
Period jitter for clock output in
fractional mode
(55)
tFOUTPJ
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output
in fractional mode
(55)
tFOUTCCJ
mUI (p-p)
ps (p-p)
Period jitter for clock output in
integer mode
(55)
tOUTPJ
mUI (p-p)
(53)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter
< 120 ps.
(54)
(55)
FREF is fIN/N, specification applies when N = 1.
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Arria 10 Devices table.
Arria 10 Device Datasheet
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