A10-DATASHEET
2015.12.31
40
DSP Block Specifications
Symbol
Parameter
Condition
Min
—
—
—
—
—
—
Typ
—
—
—
—
—
—
Max
TBD
TBD
TBD
TBD
TBD
TBD
Unit
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
ps (p-p)
mUI (p-p)
ps (p-p)
Period jitter for clock output on the
regular I/O
(59)
tOUTPJ_IO
Cycle-to-cycle jitter for clock output on
the regular I/O
(59)
tOUTCCJ_IO
mUI (p-p)
ps (p-p)
Period jitter for dedicated clock output
in cascaded PLLs
tCASC_OUTPJ_DC
mUI (p-p)
Related Information
Memory Output Clock Jitter Specifications on page 58
Provides more information about the external memory interface clock output jitter specifications.
DSP Block Specifications
Table 39: DSP Block Performance Specifications for Arria 10 Devices (VCC and VCCP at 0.9 V Typical Value)—Preliminary
Performance
Mode
Unit
–E1L, –E1M
(60), –E1S
–I1L, –
–E2L, –E2S, – –I2L, –I2S, –
–E1M (61), –
E3S, –E3V
–I1M (61), –
I3S, –I3V
I1M (60), –I1S
E2V
I2V
Fixed-point 18 × 19 multiplication
mode
548
541
548
528
522
529
456
438
364
358
370
346
344
351
MHz
MHz
MHz
Fixed-point 27 × 27 multiplication
mode
450
459
434
440
Fixed-point 18 × 18 multiplier adder
mode
(59)
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Arria 10 Devices table.
(60)
(61)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
Arria 10 Device Datasheet
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