A10-DATASHEET
2015.12.31
42
Memory Block Specifications
Performance
–I1L, –I1M (60), –I1S
Mode
Unit
–I2L, –I2S
517
Complex 18 × 19 multiplication mode
Floating point multiplication mode
Floating point adder or substract mode
Floating point multiplier adder or substract mode
Floating point multiplier accumulate mode
Floating point vector one mode
635
635
564
564
581
574
550
MHz
MHz
MHz
MHz
MHz
MHz
MHz
501
468
475
482
471
Floating point vector two mode
450
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
and set to 50% output duty cycle. Use the Quartus Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX
.
Arria 10 Device Datasheet
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