A10-DATASHEET
2015.12.31
36
Core Performance Specifications
Core Performance Specifications
Clock Tree Specifications
Table 36: Clock Tree Performance for Arria 10 Devices—Preliminary
Performance
Parameter
Unit
–E1L,–E1M (50), –E1S, –I1L,
–I1M (50), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (51), –I1M (51), –E3S,
–I3S
Global clock, regional clock, and small
periphery clock
644
644
525
644
MHz
MHz
Large periphery clock
525
525
PLL Specifications
Fractional PLL Specifications
Table 37: Fractional PLL Specifications for Arria 10 Devices—Preliminary
Symbol
Parameter
Condition
Min
30
Typ
—
Max
800
700
Unit
fIN
fINPFD
Input clock frequency
—
—
MHz
MHz
Input clock frequency to the phase
frequency detector (PFD)
30
—
fVCO
PLL voltage-controlled oscillator
(VCO) operating range
—
—
3.5
45
—
—
7.05
55
GHz
%
tEINDUTY
Input clock duty cycle
(50)
(51)
(52)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
Arria 10 Device Datasheet
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