IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
maximum count, the output pin will go low for one clock period. If both the primary and
secondary registers are enabled, the output pin reflects the state of the register in control at the
time. This generates the required waveform that is dependent on the two values in the maximum
count registers.
Because they are polled every fourth clock period, the timers can operate at a quarter of the
internal clock frequency. Although an external clock may be used, the timer output may take six
clock cycles to respond to the input.
4.18 Direct Memory Access (DMA)
DMA frees the CPU from involvement in transferring data between memory and peripherals
over either one or both high-speed DMA channels. Data may be transferred from memory to
I/O, I/O to memory, memory to memory, or I/O to I/O. DMA channels can be connected to the
asynchronous serial port.
The IA186ER supports the transfer of both bytes and words to and from even or odd addresses.
It does not support word transfers to memory that is configured for byte accesses. The IA188ER
does not support word transfers at all. Each data transfer will take two bus cycles (a minimum of
8 clock cycles).
There are four sources of DMA requests for both DMA channels:
The channel request pin (drq1–drq0)
Timer 2
The system software
Asynchronous serial port
Each channel may be programmed to have a different priority either to resolve a simultaneous
DMA request or to interrupt a transfer on the other channel.
4.19 DMA Operation
The PCB contains six registers for each DMA channel to control and specify the operation of the
channel:
Two registers to store a 20-bit source address
Two registers to store a 20-bit destination address
One 16-bit transfer-count register
One 16-bit control register
The number of DMA transfers required is designated in the DMA Transfer Count register and
may contain up to 64 Kbytes or words. It will end automatically. DMA channel function is
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