IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Reserved
09h
0ah
-
28h
–
–
–
–
–
–
–
–
–
–
–
–
–
e
0ah
0bh
0ch
0dh
0eh
0fh
10h
11h
14h
–
3
4
5
6
7
8
9
9
9
–
DMA 0 Interrupt
e
0bh
2ch
DMA 1 Interrupt
INT0 Interrupt
INT1 Interrupt
INT2 Interrupt
INT3 Interrupt
0ch
0dh
0eh
0fh
30h
34h
38h
3ch
f
10h
40h
INT4 Interrupt
f
11h
44h
Watchdog Timer Interrupt
f
14h
50h
Asynchronous Serial Port Interrupt
Reserved
15h–1fh
54h–7ch
Note: If the priority levels are not changed, the default priority level will be used for the interrupt sources.
a
Instruction execution generates interrupts.
b
Performed in the same manner as for the 8086 and 8088.
c
An ESC opcode causes a trap.
d
Because only one IRQ is generated for the three timers, they share priority level with respect to other
sources. The timers have an interrupt priority order among themselves (2A > 2B > 2C).
e
These interrupt types are programmable in slave mode.
f
Not available in slave mode.
4.17 Timer Control
The IA186ER and IA188ER each have three 16-bit programmable timers. Timer 0 and Timer 1
each has an input and output connected to external pins that permits it to count or to time events
as well as to produce variable duty-cycle waveforms or non-repetitive waveforms. Timer 1 can
also be configured as a Watchdog timer.
Because Timer 2 does not have external connections, it is confined to internal functions such as
real-time coding, time-delay applications, a prescaler for Timer 0 and Timer 1, or to synchronize
DMA transfers.
The Peripheral Control Block contains eleven 16-bit registers to control the programmable
timers. Each timer-count register holds the present value of its associated timer and may be read
from or written to whether or not the timer is in operation. The microcontroller increments the
value of the timer-count register when a timer event takes place.
The value stored in a timer’s associated maximum count register determines its maximum count
value. Upon reaching it, the timer count register is reset to 0 in the same clock cycle that this
count was attained. The timer count register does not store this maximum value. Both Timer 0
and Timer 1 have a primary and a secondary maximum count register that permits each to
alternate between two discrete maximum values.
Timer 0 and Timer 1 may have the maximum count registers configured in either primary only or
both primary and secondary. If the primary only is configured to operate, on reaching the
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